LeCroy 2366 Universal Logic Module 
を用いた BLP (Beam Line Polarimeter) 回路 I/O pin assignment
（＊）J11使用用

Bit file name : blp_c4.bit

1:input
A-01	External Clock (RF X 2 Hz)
A-02	Inverse Spin up level signal
A-03	:not used
A-04	:not used
A-05	OPR1C1:Output Resistor (OPR) No.1 Channel 1(event busy)
A-06	OPR1C2:OPR No.1 Ch.2(buffer full)
A-07	OPR1C3:OPR No.1 Ch.3(Rungate) & Inverse Veto
A-08	OPR2C1:OPR No.2 Ch.1(buffer transfer end)

CAMAC function:Trigger Sampling
wright	:vme04>nfa N 16 1 K
read	:vme04>nfa N 0  1
(*)N:station number

B-01
 |	Cave 4-pair(Left, Right, Up, Down) signal
B-08
B-09
 |	WN 4-pair(Left, Right, Up, Down) signal
B-16

2:output
C-01
 |	BLP1 (L,R,U,D)True Coin
C-04
C-05
 |	BLP1 (L,R,U,D)Chance(accidental)  Coin
C-08
C-09
 |	BLP2 (L,R,U,D)True Coin
C-12
C-13
 |	BLP2 (L,R,U,D)Chance(accidental)  Coin
C-16

D-01	TDC Start
D-02	ADC Gate
D-03	Trigger Before Veto(request)
D-04	Trigger after veto(live)
D-05	CVTRIG  Cave Trigger for IPR(Input Resister)
D-06	WNTRIG  WN Trugger for IPR
D-07	Clock Request
D-08	Clock live
D-09	Busy(for diagonostic)
D-10	Spin up? Pulse for IPR Ch.3
D-11	Spin down? Pulse for IPR Ch2.
D-12	IPR gate
D-13	j11 int1
D-14	j11 int2
D-15	rungate(OPR-1 Ch.3) level signal(for diagonostic)
D-16	Spin up(inverse)(for diagonostic)