www-server:/usr/www/docs/Divisions/np1/tamidaq/info/3hetg.txt.v1.0

  (3He,t gamma) Front End Configurations      ver 1.0
                                    07-OCT-1995  by A.Tamii

1) Coincidence Register

  Coincidence Register Bit Assign

  Coincidence Register (N=20)

   Bit  1 ... (Not Used)
   Bit  2 ... (Not Used)
   Bit  3 ... (Not Used)
   Bit  4 ... (Not Used)
   Bit  5 ... (Not Used)
   Bit  6 ... GR F.P. Trigger
   Bit  7 ... (Not Used)
   Bit  8 ... (Not Used)
   Bit  9 ... Coincidence (GR&NaI)
   Bit 11 ... (Not Used)
   Bit 12 ... (Not Used)
   Bit 13 ... (Not Used)
   Bit 14 ... (Not Used)
   Bit 15 ... (Not used)
   Bit 16 ... Block End Event

 （memo）
    GR(Bit6) and COIN(Bit9) are exclusive.

2) CAMAC Modules

 System Use

   Crate controler 
   J11 (Starburst) 
   Output Register ... Used by J11
   Coin. Register  ... Event Type

 Grand Raiden Focal Plane Detectors
   FERA(ADC)  ... #1 Virtual Station Number=1
                     ch.0-3  GR F.P. Sintillator
   TDC        ... #1 ch.0-3  F.P. Sintillator
                     ch.4    GR RF
   4299       ... #1 F.P. VDC  (Optional Pattern=1)
                     4298 #1 (Optional=0)
                     4298 #2 (Optional=1)

 NaI Detectors
   ADC        ... #1 ch.0-5 NaI
   TDC        ... #2 ch.0-5 NaI


3) CAMAC Module Station Assign

 CAMAC Crate #0

    N                     Module
    25  K3922      C.C.    Crate Controler
    24    |         |				|
    23  N/U
    22  ACC2180    J11     Starburst
    21  ?          OUT     NIM-Out
    20  ?          IN      Coincidence Register
    19  N/U
    18  N/U
    17  N/U
    16  LR4299     4299#1  Data Bus Interface (GR-VDC)
    15  N/U
    14  N/U
    13  LR2228A    TDC#1   TDC(GR)
    12  N/U
    11  N/U
    10  N/U
     9  N/U
     8  N/U
     7  N/U
     6  LR4300B    FERA#1  FERA #1
     5  LR4301     FERAD#1 FERA-Driver #1
     4  LR2228A		 TDC#2   TDC(NaI)
     3  LR2249W    ADC#1   ADC(NaI)
     2  LR2551     SCLR#1  Scaler #1
     1  LR2551     SCLR#2  Scaler #2


4) Scaler Channel Assign

    Scaler #1
      0  B.I.
      1  GR Event Request (All)
      2  GR Event Accept  (Live)
      3  GR and NaI       (Live)
      4  GR and not NaI   (Live)
      5  GR and not NaI Prescaled (Live)
      6  Clock Request    (All)
      7  Clock Accept     (Live)
      8  6 NaI's OR       (All)
      9  N/U
     10  N/U
     11  N/U

    Scaler #2

      0  NaI #1 (All)
      1  NaI #2 (All)
      2  NaI #3 (All)
      3  NaI #4 (All)
      4  NaI #5 (All)
      5  NaI #6 (All)
      6  N/U
      7  N/U
      8  N/U
      9  N/U
     10  N/U
     11  N/U

5) Event Acquistion Algorithm

    (1) read Coincidence Reigster
        clear Coincidence Register
    (2) if the 9th bit of coin. reg. is 1 (coincidence event)
        -> (GR)  read FERA  #1
        -> (GR)  read TDC   #1 ch.0-5
        -> (GR)  read 4299  #1(VDC)
        -> (NaI) read TDC   #2 ch.0-5
        -> (NaI) read ADC   #1 ch.0-5
        clear FERA, TDC #1-2, 4299, ADC
        goto 4
    (3) if the 6th bit of coin. reg. is 1 (GR single event)
        -> (GR)  read FERA  #1
        -> (GR)  read TDC   #1 ch.0-5
        -> (GR)  read 4299  #1(VDC)
        clear FERA, TDC #1-2, 4299, ADC
        goto 4
		(4) end


  (note)
    Each time when buffer is full, scaler data are accumulated (block
    end event) and scalers are cleared.