LeCroy 2366 Universal Logic Module を用いた Trigger 回路 
I/O pin assignment      31st OCT 2003 H.P.Yoshida

grc(GR+another event(SSD) mode) or glc(GR+LAS+SSD mode)

Rear LAS C Output(C1 is the first ch.)
	C1  SSD FERE2 GAte Input          
	C2  SSD FERE2 FCET Trigger        
	C3  SSD FERE2 Fast Clear          
	C4  SSD OR                        
	C5  SSD Single event(for test)    
	C6  SSD event(for IPR ch#7)       
	C7  GR FP & SSD COIN event(for grc) (GR FP timing Trigger for glc)  
	C8  SSD ADC Fast Clear Delay Gate 
	C9  SSD 3351 GAte Input           
	C10 SSD 3351 FCET Trigger         
	C11 SSD 3351 Fast Clear           
	C12 for diagonostic
	C13 SSD FERE2 Busy                
	C14 for diagonostic
	C15 SSD 3351 Busy
	C16 (SSD FERE2 Busy) OR (SSD 3351 Busy)	(OR (LAS Busy) for glc)

Check の際、C13(FERA２系統の時),C14,C16 の Busy シグナルを見てください。
13 msec かかっているようだと正しく動いていません。