-------------------------------------------- FPGA Trigger Setup (CAMAC Control) G) GR single sampling rate [1]. L) LAS single sampling rate [0]. 2) 2nd level sampling rate [0]. C) Coincidence gate width [0] ~= 25x(0+2) nsec. p) Trigger pattern 1 2 3 4 5 (plane) 1 1 0 0 0 (1:on 2:off) Q) exit --------------------------------------------